Semiconductor Integrated Circuit Layout Design (SICLD) Registration

The Semiconductor Integrated Circuits Layout Design Act 2000 gives Intellectual property protection for semiconductor IC layout designs. The Semiconductor Integrated circuits are a three-dimensional configuration of a complex layer of semiconductors, metals, dielectrics (insulators) and other materials on a substrate. The Semiconductor integrated layout registry created with the aim for promotion of Semiconductor Integrated Circuits Layout Designs in the country is the only body in India for Layout-design circuit registration. It acts as a catalyst for the intellectual property of Semiconductor Integrated Circuits Layout Designs. 

Background of the Semiconductor Layout Design

• With significant foreign investment and the rapid growth of the semiconductor industry in India, the country is now regarded as the world's leading producer of semiconductors. Taiwan, China, and Vietnam are among the top producers of semiconductors.
• According to the Semiconductor Industry Association, semiconductors are used in over 100 billion everyday items worldwide, looming over the global economy due to their higher manufacturing costs. Semiconductors are known as the brains of all electronic devices and are used in everything from internet servers to cell phones. The supply of semiconductors is still insufficient to meet demand. The main cause of this is that it takes almost three months to manufacture a semiconductor, in addition to using enormous factories, dust-free spaces, expensive equipment, etc. 
• The Semiconductor layout design registration acts as a catalyst for the development of Semiconductor Integrated Circuits layout designs' intellectual property and raises awareness of the need to protect those designs. It also serves to safeguard the intellectual property of Semiconductor integrated circuits.

Functions of the Registry Board 

• For the regulation of drawing/masking and circuit layout, the registry is located at the Department of Electronics and Information Technology's head office at Electronics Niketan, 6, C.G.O. Complex, New Delhi-110003, and it has been fully operational since May 1, 2011.
• The board safeguards the semiconductor Integrated Circuits' original layout design and any items connected to it.
• It encourages the registration of semiconductor integrated circuit layout designs' intellectual property.
• The Registry reviews the integrated circuits' layout designs and issues Registration Certificates to those that are the original designs for semiconductor integrated circuits.

The Creator receives exclusive benefits from the layout design registration, including the following:

• It safeguards the layout and design of semiconductor integrated circuits.
• It provides the exclusive right to the creator of the layout design 
• The validity of intellectual property is for ten years after which it may be further extended under certain circumstances.
• The creator gets the exclusive right to commercialize the intellectual property.
• The creator is entitled to monetary compensation and receives relief if his intellectual property rights are used without his consent or are found to have been violated.  

Government Programs and Initiatives

Numerous semiconductor manufacturing facilities have been established in India through government initiatives, and to promote the exclusivity of the intellectual layout design registration, a separate portal for the registration of such facilities has been formed. 

The Central Government has also started the following programs to increase the semiconductor manufacturing market in India:

• Plan for establishing semiconductor fabrication plants.
• Plan for assembling Display fabs.
• Arrangement plan for silicon photonic/compound semiconductor sensors. 
• Design Linked Incentive (DLI) program.

An integrated circuit layout design must satisfy the following conditions in order to be registered:

• The original layout and design of the integrated circuit for semiconductors
• The Distinctive design
• Capable of standing out from existing designs
• Have not been commercially exploited, either in India or one of the conventional countries that WIPO has approved.

The Semiconductor Integrated Circuits Layout-Design Act, which is applicable worldwide under Section 6 of the Trade Related Aspects of Intellectual Property Rights (TRIPS) Treaty of the World Trade Organization (WTO), under which the member countries have agreed to provide protection to IC layout designs, gives the registered proprietor of the layout design an inherent right to exploit and use the layout design throughout the world. India is a member country under the TRIPS Agreement.

For a person, corporation, or partnership firm to be registered as a layout-design agent, they must meet the requirements below.

• He must be a citizen of India.
• Must be at least 21 years old. 
• The applicant must possess a thorough understanding of the provisions of the act. He must pass a physical written examination in semiconductor integrated circuits layout-design law and practice, followed by an interview. He must score 40 per cent on the written exam and 60 per cent on the interview, with the combined total of both representing 50 per cent of the total marks. 
• A graduate of any university or possess an equivalent qualification 
• The government believes that a person is qualified and suitable to be registered as a layout-design agent.

Persons Prohibited from Semiconductor Integrated Circuit Layout Design Registration

The following categories of individuals are not permitted to register as layout design agents: 

• Declared as Unsound mind by any competent court
• Declared as undischarged insolvent.
• Or discharged insolvent but has not yet been declared by the competent court that insolvency was caused by misfortune without any misconduct on his part.
• Convicted by a competent court with an offense punishable with imprisonment, unless the offence has been convicted or pardoned on the application made by him, or the central government has removed his disability.
• Being a legal practitioner has been held guilty of professional misconduct by the High Court in India or by any court beyond the limits of India.
• Being a CA has been held guilty of negligence or misconduct by a High Court.

The Semiconductor Integrated Circuits Layout-Design Act of 2000's Section 96, subsections (1) and (2), defines the procedure for filing an application for an integrated circuit layout design at the Semiconductor Integrated Circuits Layout-Design Registry (SICLDR). 

• The registered office is at the Department of Electronics and Information Technology, 6 CGO Complex, Lodi Road, New Delhi-110003, and is accessible to applicants from all over India. 
• The application must be submitted using the template provided for the registration of layout designs (Form LD-1) by the creator of the layout design or the person who wishes to register his or her intellectual layout design.
• The layout design's title should be specified.
• The applicant's full name, nationality, company name, country of incorporation, or partners' names, if applicable,
• Address information for the main office in India.
• The specifics, including the structure of the layout, the methods used, and the design's functions. 
• A brief description of the layout-design declaration that it has not been commercially exploited and a description of the location of any exploitation, including the name of the country, the date, and the year, if any.
• The application must be submitted to the Registry at the above-mentioned registered address, and the Registry may accept or reject the application. 
• Within 14 days of acceptance, the application must be advertised. Opposition has three months to file their opposition, and the counter statement must be filed within two months of the date they received the registrar's notice of opposition.
• The Registrar will decide whether to accept or reject the application after hearing from both parties.

The applicant must specifically provide the following details about the integrated circuit (IC) that was created using layout-design when submitting an application for layout design registration. 

• Structure details like Bipolar, MOS, Bi-MOS, Optical IC, or other specifications.
• Technical details like TTL, DTL, CMOS, NMOS, PMOS, or other Specification.
• The Functional details such as Logic, Memory, Linear, Microcomputer
• Layout Design photograph or drawings (3 sets) (paper size 33cm/20cm)
• Semiconductor Integrated circuits (4 pieces)
• Photographs of mask layout used for the fabrication of the semiconductor integrated circuit by using layout design.
• Fee details 
• Other details as per the specifications of the layout design registration.
• The signature of the applicant or his authorized representative being a legal practitioner or registered layout-design agent or person in the sole employment of the applicant.

If the applicant is willing to keep the layout design's secrecy, he must attach three sets of blocked drawings of the layout design that satisfy the Registrar in place of a photograph or drawing.

To register a layout design, the applicant must pay a registration fee of Rs. 5,000, which is non-refundable if an application error is found. However, the layout-design agent must pay Rs. 1000 on April 1 of every year to maintain the blocked-out portion of such a drawing or photograph and to keep his name on the register of layout-design agents.  

Validity of SICLD Registration

The Semiconductor Integrated Circuits Layout Design Registry registration is valid for ten years after the date of registration, which can be further extended under certain circumstances.